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Three methods of bare chip attachment to the substrate are as follows: 1. Wire-bonding is the oldest and the most flexible and widely used method. (More than 96 percent of all chips today are wire-bonded.) 2. Tape-automated bonding (TAB) is useful with small I/O pitches and provides the ability to pretest the chips before assembly. 3. Flip-chipping is used for its compactness and improved electricals, typical of which is the C4 process of IBM. The problems of thermal coefficient of expansion (TCE) mismatch between silicon chips that are directly flip-chipped onto a laminate substrate have been effectively eliminated by using a filled epoxy underfill encapsulation technique between the chip and the substrate (see

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Printing QR Codes within your Crystal Reports - The Crystal Reports ...
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Fig. 2.5). This method distributes stresses over the entire area of the chip and thus significantly improves the reliability performance of this assembly method. While the chips that need area array or flip-chip terminations i.e., those with high pin counts are the fastest-growing category of ICs, they still represent only a very small percent of all ICs used. Designers must, therefore, ascertain which of the DCA methods will be the most cost beneficial for a particular application.

Chip-Scale Packages (CSPs)

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When mounting unpackaged chips on these interconnecting substrates, it is not always possible to ascertain that only properly operating chips have been assembled. By now, there are a number of methods proposed to solve this known good die (KGD) problem. As one of the ways to resolve this problem, a number of manufacturers have developed a set of miniature packages, only slightly larger than the chip itself, which protect the chip and redistribute the chip termination to a grid array. These miniature packages permit testing and burning in of chips prior to their final assembly. A typical example of such chip scale packages is shown in Fig. 2.6. There are a number of such packages on the market.

We say a connection metric vanishes:

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The designer, however, must analyze the termination pitches of these new CSPs because some use very tight grids, such as 0.5 mm (0.020 in) or less, which need special PWB techniques to permit signal redistribution from these packages to the rest of the board. In general, the current PWB technology is adequate to provide direct chip terminations if wire-bonding or TAB techniques are used for interconnecting bare chips to the substrate. It requires placing suitable bonding pads spaced by the required pitch in one or two rows around the chip site. While this somewhat reduces the packaging efficiency of the board, it is still an effective method for DCA assemblies. With grid array, the situation is more difficult because the signals from internal rows of area grid terminations must be routed between the terminals located closer to the edge, which

do not permit more than one, or at most two, conductors to pass through. In most cases, these signals from internal rows are brought down into internal layers of MLBs. The conventional PCB constructions today cannot handle any grid arrays with pitches below 0.020 in, while some flip-chip ball grid arrays go below 0.010-in pitch. In cases when grid distances of the area terminations are below 0.50 mm (0.040 in), special redistribution layers are frequently used, which distribute signals to the conventionally made PTHs in supporting MLB. Such layers consist of unsupported dielectric layers where small vias or blind holes are formed by laser or plasma etching or are photoformed and then plated using additive or semiadditive metallization processes. While this approach requires some extra area beyond the chip perimeter to complete the signal transfer and increases the costs of substrates, it permits the mounting of flip-chips and CSPs on PWBs. A typical method for forming such redistribution layers, called surface laminar circuit (SLC),4 has been developed at IBM s Yasu plant.

CAD Formats The leading CAD system vendors have created several formats. When there is a high level of cooperation between customer and supplier, the design customer can send the whole design database from the CAD system on which it was created (and achieve the goal of intelligent exchange as depicted in Fig. 18.3). CAD formats are excellent for testing assembled boards because they include the schematic information. In addition, they include component locations and packages, as well as enough data to derive the graphics of any board layer. They must be accompanied by BOM information and also AVL information (unless parts are consigned) to define which components to place for each board variant and which components to procure. CAD formats are less suitable for board fabrication, because they lack a flattened WYSIWYG ( what you see is what you get ) representation of the circuit layers. Examples of CAD formats include Mentor s Board Station Neutral and Geoms files, as well as Cadence or ORCAD layout files. When CAD formats are used for data exchange, their format is, by definition, the format of the specific CAD system that was used for layout and routing. The designer must therefore verify that the supplier can read it or use some translation tool to convert the data to a format readable by the supplier, risking conversion errors.

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