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Balancing the Density Equation With the need for more parts on an assembly and the trend to make things smaller for portability or faster speeds, the design process is a challenging one. The process is one of balancing the density equation with considerations for certain boundary conditions such as electrical and thermal performance. Unfortunately, many designers do not realize that there is a mathematical process to determine the routing rules of a printed circuit. Let me briefly explain. The density equation, as seen in Eq. 19.2 and Fig. 19.10, has two parts: the left side, which is the component wiring demand, and the right side, which is the substrate wiring capability. Component PWB Wiring Demand < PWBs Design Rules & Construction Wiring Capabilities where (19.2)

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PWB Wiring Demand = total connection length required to connect all the parts in a circuit PWB Wiring Capability = substrate wiring length available to connect all the components

Four conditions can exist between wiring demand and substrate capability:

Wiring Demand > Substrate Capability If the substrate capacity is not equal to the demand, the design can never be finished. There is not enough room for either traces or vias. To correct this, either the substrate has to be bigger or components have to be removed. Wiring Demand Substrate Capability Although theoretically optimum,this condition leaves no room for variability and it would take an unacceptable amount of time to complete the design.

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Wiring Demand < Substrate Capability This condition should be your goal. There should be enough extra capacity to complete the design on time with only a minimum of over specification and costs. Wiring Demand << Substrate Capability This is the condition that usually prevails. By PCB layout, the schedule is tight and timing is all important. Many choose tighter traces or extra layers to help shorten the layout time. This increases the manufacturing costs 15 to 50 percent higher than is necessary, which is sometimes called the sandbag approach. It is unfortunate, as the preceding models would help to create a better-planned environment.

Wiring Demand (Wd) Wiring demand is the total connection length (in inches) required to connect all the parts in a circuit. If the design specifies an assembly size (in square inches), then a wiring density in inches per square inch or centimeter per square centimeter is created. Models early in the design planning process can estimate the wiring demand. Three cases can control the maximum wiring demand:

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The wiring required to break out from a component such as a flip chip or chip scale package The wiring created by two or more components tightly linked, such as a central processing unit (CPU) and its cache or a digital signal processor (DSP) and its input/output (I/O) control The wiring demanded by all integrated circuits and discretes collectively

Models are available to calculate the component wiring demand for all three cases; see Sec. 19.4.3. Since it is not always easy to know which case controls a particular design, it is usually to calculate all three cases to see which one is the most demanding and thus controls the layout. Wiring demand is defined by Eq. 19.3. Wd = Wc e (in cm/square cm or in./square in.) where Wd = Wiring Demand Wc = Wiring Capacity e = PWB Layout Efficiency (determined in Sec. 19.4.3) (19.3)3

Wiring Capacity (Wc) Substrate wiring capacity is the wiring length available to connect all the components. It is determined by two factors:

Design rules These rules specify the traces, spaces, via lands, keepouts, and such that make up the surface of the substrate. Structure This factor determines the number of signal layers and the combination of through and buried vias that permit interconnection between layers and the complex blind, stacked, and variable depth vias available in high-density interconnection (HDI) technologies.

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These two factors determine the maximum wiring available on the substrate. To figure the wiring available to meet the demand, multiply the maximum wiring by the layout efficiency. The data are straightforward except for layout efficiency. Layout efficiency expresses what percentage of wiring capacity can be used in the design. Equation 19.4 shows the formula for determining wiring capacity for each signal layer. The total substrate capacity is the sum of all the signal layers. Wc = T L/G (in cm/square cm or in./square in.) where T = number of traces per wiring channel or distance between two via pads L = number of signal layers G = wiring channel width or length between centers of the via pads (19.4)

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