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Complexity x1 1.14E+06 2.01E+06 1.49E+04 5.46E+05 1.62E+05 2.17E+06 8.00E+06 4.77E+06 5.60E+06 1.08E+07 6.40E+04 1.27E+04 2.72E+03

3. 4. 5. 6.

Calculate the board complexity index and average yield. Prepare a spreadsheet of transformed CI (x1) and Yield (Y) (see Table19.6) Calculate regression coefficients (see Table 19.7). Calculate A and B from regression fits.

The Ricci tensor is symmetric, so Rab = Rba . Using contraction on the Ricci tensor, we obtain the Ricci scalar R = g ab Rab = R a a (4.47)

19.5.2.3 PCB Part Information. Collect design attributes of 10 to 15 currently running boards with various size and layers (see Table 19.3). 19.5.2.4 PCB Production Yield Data. Collect the first-pass yield information for these selected boards, for at least 10 runs (see Table 19.5)

TABLE 19.5 Example of PCB Production Yields from 10 Runs P/N Run #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 First pass yield (at Electrical test) 1 92.6 85.6 95.6 92.3 94.8 86.8 90.3 89.3 87.2 86.6 92.7 93.8 99.2 2 84.9 85.7 93.9 93.3 97.6 85.3 80.9 87.0 87.9 88.1 92.7 95.3 98.6 3 86.9 94.2 93.6 95.0 96.4 88.1 86.3 86.6 86.6 82.6 97.2 98.2 99.1 4 82.9 86.2 97.8 92.6 96.6 90.8 87.9 83.5 85.7 84.4 95.1 96.3 98.7 5 90.0 86.6 97.3 94.5 94.1 86.5 87.1 91.6 89.4 88.0 96.9 94.1 97.9 6 95.2 86.7 95.1 95.5 93.2 87.0 92.7 90.1 87.3 87.0 94.3 95.9 99.6 7 90.1 86.6 94.2 93.5 94.3 88.0 87.3 87.5 90.6 79.0 93.4 94.2 99.6 8 92.4 89.7 96.2 89.7 93.2 87.2 87.6 86.2 86.5 87.0 95.3 92.3 99.1 9 93.0 95.6 96.9 88.8 91.8 86.5 82.4 88.1 85.9 88.0 91.6 94.8 99.0 10 92.0 85.6 91.6 89.8 91.2 88.9 88.9 87.3 82.9 80.0 96.6 95.6 99.3

Component Density Analysis Because the components and their terminations exert a major effect on the design of the PWB, a number of metrics have been developed to establish the relationships between component density and PWB density.A major analysis of these relationships has been made by H. Holden5 and some of his charts and derivations are provided here to guide the design engineers during the development of a rational PWB design. This information is very useful in determining where the designed product will fit in the component density spectrum and what, therefore, is to be expected for PWB density. Figure 2.7 provides a generalized view of the relationships among the component density, their terminal density, and the necessary wiring density that will be required to accommodate the selected degree of component complexity. The definition of the wiring connectivity Wf is provided.

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PWB Density Metrics It is essential for the proper design of PWBs to determine the density requirements and then analyze alternative methods of board construction for the most cost-effective design. There are a number of basic terms and equations used for the calculation and analysis of PWB wiring density.

(2.1)

But it is more important to determine the required wiring density that will be sufficient to interconnect all the components on the desired board size. There have been a number of empirically developed equations that permit the calculation of such a wiring demand. The simplest has been developed by Dr. D. Seraphim:6 Wd = 2.25 Nt*P where Wd = wiring demand Nt = number of I/Os P = pitch between packages 2.6.3 Special Metrics for Direct Chip Attach The assembly of uncased or bare chips on substrates has become popular mostly due to the ability of such assemblies to reduce the area of interconnections. The ideal limit for such assembly would be to place all the chips tightly together, without any space in between. This would result in 100 percent packaging efficiency, a metric measuring the ratio of silicon area to the substrate area. Naturally, such 100 percent efficiency is not achievable, but this metric is still useful in ranking various substrate construction or bare chip attachment methods, as shown in Fig. 2.8. (2.2)

Packaging efficiency. (Courtesy of BPA, used with permission.)

Packaging efficiency of 100 percent is impossible to achieve because all chip-mounting methods require some space around the chips. Even with flip-chips, there must be a distance left between the chips to permit room for the placement tool.